3D-Integrated 2-Megapixel Imager with Sparse Capture and Fine-Grain Power Gating
Abstract
This paper presents a 3D integrated 2-megapixel image sensor with programmable sparse capture, fine grain power gating, and block-parallel ADC architecture. A combination of row-, column-, and block-level power gating are combined to minimize energy and readout latency for each frame based on a set of pixels requested by upstream vision algorithms. We demonstrate >7x reduction in frame energy and readout latency for representative sampling patterns.
Citation
A. Berkovich et al., “A 3D-Integrated 2-Megapixel Imager with Sparse Capture and Fine-Grain Power Gating,” 2023 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023, pp. 1-4, doi: 10.1109/IEDM45741.2023.10413713. keywords: {Image sensors;Three-dimensional displays;Electron devices},